The present invention relates to the manufacture of very large scale integrated (VLSI) circuit designs and more specifically relates to generating phase shifted mask designs.
A very large scale integrated (VLSI) complementary metal oxide semiconductor (CMOS) chip is manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc.). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations has to be confined to small, well defined regions.
Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending with the removal of the expended photoresist to make way for the new resist to be applied for another iteration of this process sequence.
The basic lithography system consists of a light source, a stencil or photo mask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The aligning may take place in an aligning step or steps and may be carried out with an aligning apparatus. Since a wafer containing from 50 to 100 chips is patterned in steps of 1 to 4 chips at a time, these lithography tools are commonly referred to as steppers. The resolution, R, of an optical projection system such as a lithography stepper is limited by parameters described in Raleigh""s equation:
R=kxcex/NA,
where xcex represents the wavelength of the light source used in the projection system and NA represents the numerical aperture of the projection optics used. xe2x80x9ckxe2x80x9d represents a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from about 0.8 down to about 0.5 for standard exposure systems. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 248 nm. Wavelengths of 356 nm are also in widespread use and 193 nm wavelength lithography is becoming commonplace.
Conventional photo masks consist of chromium patterns on a quartz plate, allowing light to pass wherever the chromium has been removed from the mask. Light of a specific wavelength is projected through the mask onto the photoresist coated wafer, exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to light of the appropriate wavelength causes modifications in the molecular structure of the resist polymers which, in common applications, allow a developer to dissolve and remove the resist in the exposed areas. Such resist materials are known as positive resists. (Negative resist systems allow only unexposed resist to be developed away.) The photo masks, when illuminated, can be pictured as an array of individual, infinitely small light sources which can be either turned on (points in clear areas) or turned off (points covered by chrome). If the amplitude of the electric field vector which describes the light radiated by these individual light sources is mapped across a cross section of the mask, a step function will be plotted reflecting the two possible states that each point on the mask can be found (light on, light off).
These conventional photo masks are commonly referred to as chrome on glass (COG) binary masks, due to the binary nature of the image amplitude. The perfectly square step function of the light amplitude exists only in the theoretical limit of the exact mask plane. At any given distance away from the mask, such as in the wafer plane, diffraction effects will cause images to exhibit a finite image slope. At small dimensions, that is, when the size and spacing of the images to be printed are small relative to the xcex/NA, electric field vectors of adjacent images will interact and add constructively. The resulting light intensity curve between the image features is not completely dark, but exhibits significant amounts of light intensity created by the interaction of adjacent features. The resolution of an exposure system is limited by the contrast of the projected image, that is, the intensity difference between adjacent light and dark image features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than discrete images.
The quality with which small images can be replicated in lithography depends largely on the available process window; that is, that amount of allowable dose and focus variation that still results in correct image size. Phase shifted mask (PSM) lithography improves the lithographic process window or allows operation at a lower k value by introducing a third parameter on the mask. The electric field vector, like any vector quantity, has a magnitude and direction, so, in addition to turning the electric field amplitude on and off, it can be turned on with a phase of about 0xc2x0 or turned on with a phase of about 180xc2x0. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material. By recessing the mask to an appropriate depth, light traversing the thinner portion of the mask and light traversing the thicker portion of the masks will be 180xc2x0 out of phase, that is, their electric field vector will be of equal magnitude but point in exactly the opposite direction so that any interaction between these light beams result in perfect cancellation. However, because the 180xc2x0 phase transition forces a minimum in the image intensity, narrow dark lines will be printed. These unwanted residual phase images are erased using a trim mask, which is a second mask that transmits light only in regions left unexposed by the residual phase edge.
Alternating Phase Shifted Mask (altPSM) lithography is a resolution enhancement technique that is rapidly gaining acceptance as a viable solution to meet aggressive integrated circuit (IC) technology scaling time-lines. Delays in next generation optical and non-optical lithography tooling add vital importance to successful implementation of altPSM. AltPSM takes advantage of destructive interference of light to double the achievable resolution of an optical lithography system. The light interference is created by selectively manipulating the topography of the photomask to introduce an appropriate path-length difference in the imaging light. In a typical altPSM design, a circuit element that has a layout dimension that is less than a cutoff dimension is selected for phase shifting. The cutoff dimension is related to the resolution of the lithography system and a layout dimension that is less than this cutoff is referred to hereinafter as a sub-cutoff layout dimension. The design of the altPSM involves disposing phase shifting shapes on opposing sides of the sub-cutoff dimension, where one phase shape is assigned a phase shift that is 180xc2x0 out of phase from that of the opposing phase shape. Thus, layout decisions must be made regarding the size, spacing, and phase assignment of these phase shapes relative to the layout of circuit elements. This manipulation of the mask topography requires phase information to be added to the circuit layout in the computer-aided design (CAD) system. Key to the successful implementation of altPSM is an efficient electronic design automation (EDA) tool that can convert circuit designs to altPSM layouts with minimal impact to layout design density or design complexity.
FIGS. 1A-1D illustrates typical steps used in an altPSM manufacturing process. FIG. 1A illustrates a standard COG mask including a transparent substrate 10 (e.g. quartz) overlain by opaque regions 20, typically chrome. The opaque regions 20 are formed by depositing a layer of opaque material, such as chrome, over the transparent substrate 10, depositing and patterning a first resist layer (not shown) over the opaque layer, and then etching the opaque layer to form the patterned opaque regions 20. Then a second layer of resist 30 is deposited and patterned to form resist openings 15 corresponding to phase regions to be etched as illustrated in FIG. 1B. Note that the openings 15 in the second resist layer are wider than the openings in the chrome patterns by about xc2xd the minimum feature width in a self-aligned process. The mask substrate 10 is then etched selective to chrome to a target phase depth, forming the phase regions 120 (typically 180xc2x0 phase regions), and the second resist layer is removed, resulting in the structure illustrated in FIG. 1C, where the unetched regions 110 are 0xc2x0 phase regions. An isotropic etch-back of the substrate 10 may be used to compensate for edge shadowing effects, resulting in the final mask structure illustrated in FIG. 1D.
The generation of an altPSM layout requires the addition of phase shapes on opposing sides of layout features that have dimensions smaller than a cutoff dimension (Dcut) related to the resolution of the lithography system, referred to hereinafter as a sub-cutoff layout dimension. For example, FIG. 2 illustrates a schematic of a typical transistor altPSM layout. The transistor feature 100 includes a line having a sub-cutoff layout dimension (LW), which is defined on the altPSM layout with 0xc2x0 phase region 110 and 180xc2x0 phase region 120. In addition to being assigned opposite phases, these phase shapes or regions need to obey a variety of lithographic, mask manufacturability, and design rules governing their size and spacings. Some rules are mutually opposing and require careful optimization.
Methods to assign and optimize phases in an altPSM design are known in the art. For example, referring to FIG. 8, after creating an initial circuit layout (Block 901), the design of the altPSM (Block 900) is performed. Critical circuit elements having sub-cutoff layout dimension LW are identified, as indicated in Block 910 of FIG. 8. Phase shapes are defined in association with each critical element (Block 920). Then the phase shapes are legalized according to the various rules as discussed above (Block 930). Next, the appropriate phases are assigned to each phase shape (Block 940), ensuring binary coloring across the entire mask layout. The process of defining portions of the mask as 0xc2x0 phase regions and other portions as 180xc2x0 phase regions is generally referred to as phase coloring. Techniques for automatic phase coloring are known. For example, Kim et al. (U.S. Pat. No. 5,883,813) describes a method for automatically assigning binary properties, such as phase coloring, to a network of elements, such as a the elements of a VLSI circuit design, or other networks of elements. In the method of Kim et al., nets are defined to include coupled intrusion pairs of elements. An intrusion pair is defined so that when one element is assigned one of the two binary properties of interest, the second element of the intrusion pair is assigned the other binary property. In the case of an altPSM design layout, the intrusion pairs are phase shapes, where the phase of one shape determines the phase of the other shape within each intrusion pair. The intrusion pairs are shapes that are close enough that light passing through the shapes will interact and affect the image intensity between the shapes. Thus, intrusion pairs that are sufficiently close together will likewise interact and will be coupled together by a xe2x80x9cconnectedxe2x80x9d function that defines a net. Nets are defined by intrusion pairs that have common elements assigned according to the xe2x80x9cconnectedxe2x80x9d function. As each intrusion pair is assigned to a net, the net is checked for any coloring conflicts or violations of the xe2x80x9cconnectedxe2x80x9d function so that all elements assigned to a net satisfy the xe2x80x9cconnectedxe2x80x9d function. All intrusion pairs, i.e. phase shapes in the case of an altPSM design, within a net will be colored together such that each element of an intrusion pair is assigned an opposite binary property from its paired element. For example, phase shapes would be assigned alternate phase shifts across each critical element dimension in an altPSM design. The technique of Kim et al. can be applied to both dark-field and light-field PSM designs, and can be adapted to both flat and hierarchical VLSI CAD databases. After the phases have been assigned to the phase shapes within each net in conformance with the xe2x80x9cconnectedxe2x80x9d function and other rules, the layout is checked for any inconsistencies or errors (Block 950). If layout conforms with all rules, then the altPSM design is accepted and the associated trim mask is then designed (Block 909). Although it may not be possible to correct all such errors, the layout may be acceptable, even though it might not be optimal. For example, a layout that might otherwise be acceptable could have a narrow process window. In other cases, however, it may be necessary to re-design the circuit layout (Block 960).
The xe2x80x9cconnectedxe2x80x9d function that is used to define phase shape intrusion pairs in altPSM designs may be typically expressed by a cutoff dimension for layout widths. If the width of a circuit element in the altPSM layout is smaller than the cutoff dimension, then that feature will be laid out with phase shifting shapes disposed on opposing sides of that feature dimension. This rule thus constrains the design of the mask layout. Other rules may also place additional constraints on the layout, but may be of lesser significance in the mask design or the resulting image, but could nonetheless improve overall quality or reduce costs if the layout conformed to such rules. On the other hand, the violation of some rules in a design could significantly impact the quality of the resulting product and those rules should typically not be violated. Thus, it would be desirable to provide a method that can handle such additional rules while also taking into account the relative importance or priority of the rules.
One example of an additional altPSM design rule is the rule for minimum phase-to-phase spacing. If two phase shapes approach each other to within a given spacing, the space must be eliminated by filling and merging the two phase regions. The problem is illustrated by reference to FIGS. 3-7 and is described in the following discussion. In each of these figures, part A illustrates a top down view of two nets (as defined in Kim et al. described above) of an altPSM layout, and parts B-D illustrate cross-sections of the corresponding mask at three steps in the process of manufacturing the mask. FIG. 3A shows a top down view of two neighboring nets 310 and 320 of an alternating phase shift mask layout, each net including a feature 100 having a sub-cutoff layout dimension LW. Net 310 has a 180xc2x0 phase region 120 to the left of critical feature 100 and a 0xc2x0 phase region 110 on the left of feature 100. Net 320 has a 0xc2x0 phase region on the left and a 180xc2x0 region on the right of feature 100. Thus, in this example, the two 0xc2x0 phase regions, each having widths dp, are adjacent to each other, separated by a distance ds which is larger than LW. The nominal phase widths dp are typically assigned a predetermined, fixed width. FIG. 3B illustrates the corresponding cross-section of the mask after the patterning and etching of the chrome layer 20 to provide openings corresponding to the transparent phase regions. The mask substrate 10 is commonly quartz. Typically, an anti-reflective coating (ARC) 25 has also been formed over the chrome layer 20 and similarly etched. A second layer of resist 30 is applied, and patterned to form openings 15 in the resist layer 30 to etch the 180xc2x0 degree phase regions as illustrated in FIG. 3C. Note that each of the openings 15 have a width do that is wider than the width dp of the phase regions 120 in a self-aligned process. For a self-aligned process, if the opening 15 is centered over the 180xc2x0 phase shape 120, the opening 15 should be wider than the phase shape 120 by a self alignment tolerance distance dd equal to d1, plus d2, as illustrated in FIG. 6C. Assuming that d1, and d2 are equal, a suitable value for d1, and d2 is about xc2xd Dcut (the cutoff dimension), so that, assuming that the phase width dp is equal to about Dcut, the width do of the opening 15 will be about 2xc3x97Dcut. Although it may be convenient to set the self alignment tolerance dd (the sum of d1, plus d2) and the phase width dp equal to Dcut, other values for dd and dp may be selected according to design requirements. The quartz substrate 10 is then etched selective to chrome, and the resist is removed, resulting in the mask structure of FIG. 3D having a 180xc2x0 phase regions 120 and 0xc2x0 phase regions 110. As long as the width dc of the chrome feature 27 is larger than or equal to a minimum distance, dcmin, this mask is manufacturable.
However, if the distance, for example ds between nets 410 and 420 as illustrated in FIG. 4A, between like phase regions of neighboring nets becomes smaller than a minimum distance dcmin, the narrow chrome lines such as feature 27xe2x80x2 having width dc smaller than dcmin are difficult to manufacture reliably. For high resolution processes, where Dcut is close to the mask process resolution limit, the minimum width dcmin of chrome lines that can be manufactured is in the range about 0.5-0.8xc3x97Dcut, and typically about 0.7xc3x97Dcut. The typical solution is to merge phase regions that are closely spaced to form one large phase region 110 having a width dM as illustrated in FIG. 4C. The process of ensuring that phase regions meet chrome manufacturability rules is part of the step 930 of legalizing phase shapes in conventional methods for designing altPSM layouts as illustrated in FIG. 8.
After the step of legalizing phase shapes (Block 930), a conventional altPSM design flow proceeds to a step of assigning phase shift (Block 940) to the phase shapes. In this step, the assignment of phases are constrained by an additional manufacturability constraint that can complicate the design process. The phase shift regions are formed on the mask by a patterned etch. The manufacturability of these phase regions is partly constrained by the manufacturability of resist features formed in the patterning of the phase shift regions. This problem can be better understood by reference to FIGS. 5, 6 and 7.
FIG. 5A illustrates the case of a net 510 having a 180xc2x0 degree region 120 which adjacent to a 0xc2x0 degree phase region 110 of a neighboring net 520 separated by a distance ds. Typically, such a phase coloring is not a problem because a mask as illustrated in FIG. 5D having an etched phase region adjacent to an unetched phase region does not tend to cause manufacturability problems as long as the separation distance ds is equal to or larger than the minimum width dcmin, (between about 0.5-0.8xc3x97Dcut, and typically 0.7xc3x97Dcut) so that the chrome feature 27 has a width dc, greater than dcmin as discussed above.
However, a manufacturability problem can occur in the case where there are two 180xc2x0 degree phase regions adjacent to each other. Referring to FIG. 6A, two neighboring nets 610 and 620 are phase colored such that corresponding 180xc2x0 degree phase regions 120 are adjacent to each other, separated by a distance ds. FIG. 6B illustrates the cross-section after the second resist layer 30 has been applied. A problem arises at the step of forming resist openings 15 for etching the 180xc2x0 degree phase regions 120. The width do of the resist openings 15 are larger than the width dp of the desired 180xc2x0 degree phase regions 120 for self-alignment purposes by a combined self-alignment tolerance distance of dt=d1+d2. If the opening 15 is centered on the phase shape 120, then typically d1, and d2 are chosen to be about 0.5xc3x97Dcut, and dt=Dcut, which results in a resist opening 15 having width of do=dp+Dcut. However, this can lead to the formation of a resist feature 37 that has a small width dr that is smaller than a minimum resist width Rmin that is difficult to manufacture and causes inspection problems. Rmin may be in the range from about 0.5-0.8xc3x97Dcut, and is typically about 0.7xc3x97Dcut. This means that the distance ds between two adjacent 180xc2x0 phase shapes must be wider than a minimum distance dpmin of about dt+Rmin, or typically dpmin is about 1.7xc3x97Dcut. The conventional solution to the situation where ds is less than dpmin is to merge the adjacent 180xc2x0 degree phase regions 120 of FIG. 6A into one large 180xc2x0 degree phase region 120xe2x80x2 having a width dpm, as illustrated in FIG. 7A. Note that the nets 610 and 620 are now effectively merged into a combined net 730. A self-aligned resist opening 15xe2x80x2 is formed having a width doxe2x80x2=dpmin+dt and the substrate is etched to form the merged 180xc2x0 phase region 120xe2x80x2, resulting in the altPSM cross-section illustrated in FIG. 7D.
Note that the minimum 180xc2x0-180xc2x0 distance dpmin (about 1.7xc3x97Dcut) to ensure resist manufacturability is larger than the minimum 0xc2x0-0xc2x0 spacing distance dcmin, (about 0.7xc3x97Dcut) required to ensure chrome manufacturability as discussed above. One way to enforce the minimum 180xc2x0-180xc2x0 distance dpmin is to require that all adjacent net phases meet the dpmin requirement in legalization step 930 of FIG. 8. However, because dpmin is significantly larger than dcmin, this can significantly impact the design of the mask layout and alter the density of the design. Since phase assignments conventionally occur in a subsequent step 940 after an initial legalization step 930, the enforcement of the minimum 180xc2x0-180xc2x0 phase spacing distance dpmin or a merger of adjacent 1800-180xc2x0 phase shapes would require additional iterations of steps 920 and 930 and increase the complexity in the design process flow of an altPSM layout.
Many other design rules can be found that constrain the design with different degrees of impact on the design.
In view of the foregoing discussion, there is a need to provide for a method for designing an alternating phase shifted mask (altPSM) that accounts for multiple design rules that may have differing impact on the design and differing degrees of importance or priority with respect to the acceptability of the design. For example, a design criterion that avoids adjacent etched phase shapes (for example, the 180xc2x0-180xc2x0 phase regions) having spacings that violate mask manufacturability rules is desirable because it maximizes layout density and minimizes the complexity in the design process flow, but such a rule will typically have a lower design priority than the rules governing the image resolution of critical circuit elements. There is also a need to implement a method that incorporates rules having differing priorities into existing software methodologies for designing altPSM layouts.
The present invention addresses the above-described need by providing a method for optimizing the design of an alternating phase shifted mask (altPSM) that assigns phase shapes and phase coloring according to a hierarchical set of rules or relationships. More generally, the present invention provides a method for automatically assigning binary properties to the elements of a very large semiconductor integrated (VLSI) circuit design layout according to a prioritized set of rules.
In a preferred embodiment, the present invention addresses the above-described need by providing a method for optimizing the design of an alternating phase shifted mask (altPSM) so that manufacturability constraints are met.
It is the further object of the present invention to provide a method for optimizing the design of an alternating phase shifted mask (altPSM) so that an additional set of design rules, such as manufacturability constraints, are met without significantly impacting layout density.
This invention has the further objective of providing a method of optimizing the design of an altPSM that incorporates additional design constraints, such as ensuring mask manufacturability, without significantly increasing the complexity of the altPSM design flow.
In accordance with one aspect of the present invention, a method is provided for assigning binary properties to elements of a VLSI circuit or network layout according to a set of rules having differing priorities and assigning the binary properties in a hierarchical manner from the highest to lowest priority rules. The method defines intrusion pairs of layout elements according to sets of rules, functions, or relationships in decreasing priority order. Intrusion pairs and net coloring according to lower priority rules are defined as long as higher priority rules are not violated. Violations of lower priority rules may be allowed in preference to higher priority rules. The method is applicable for generating alternating phase shift mask (altPSM) designs from VLSI CAD datasets.
In accordance with one aspect of the present invention, a method for designing an alternating phase shifting mask (altPSM) includes identifying critical elements of a circuit layout having a sub-cutoff dimensions, generating an initial set of phase shapes disposed on opposing sides of each sub-cutoff dimension, legalizing the phase shapes in accordance with chrome manufacturability criteria, including merging adjacent phase shapes where chrome lines would violate the manufacturability criteria, assigning phase shifts to the legalized phase shapes, and then ensuring that there are no spacings between etched phase shapes of neighboring nets (e.g. 180xc2x0 phase assignments) that have spacing less than an etching manufacturability constraint. In accordance with the present invention, if such spacings exist, the solution is to reverse the phase colorings in the adjacent net so that the 180xc2x0-180xc2x0 spacing violation no longer occurs.
In accordance with another aspect of the present invention, the etching manufacturability constraint includes a minimum resist width, and further includes the case where the minimum resist width is about 0.5-0.8 times a cutoff dimension, where the cutoff dimension is the maximum layout dimension that requires phase shifting.
In accordance with another aspect of the present invention, the etching manufacturability constraint includes a requirement that the first net edge and the second net edge be separated by a distance greater than the sum of an etching alignment tolerance and a minimum resist width. The method includes the case where the etching alignment tolerance is about the cutoff dimension and the case where the minimum resist width is about 0.5-0.8xc3x97the cutoff dimension.
According to another aspect of the current invention, a computer program product is described for performing the generalized coloring method and for an embodiment of the method as described above for designing an alternating phase shifting mask (altPSM) and which can be incorporated as a module within existing computer programs for desiging altPSM layouts.